Method of manufacturing a semiconductor device

ABSTRACT

The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of Ser. No. 12/855,906 filed on Aug. 13,2010, which is a division of Ser. No. 12/323,614 filed on Nov. 26, 2008,which claims priority to Japanese patent application No. 2007-309937.The content of each of these applications is hereby expresslyincorporated by reference

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method ofmanufacturing a semiconductor device.

In a conventional process of manufacturing a semiconductor device, thereis adopted a method of forming trenches and via holes in an insulatingfilm by etching, embedding metal layers in the formed the trenches andthe via holes and forming interconnect.

Shapes of the trenches and the via holes (hereinafter referred to as“trenches or the like”) are conventionally controlled based on anetching time, but the control based on an etching time involves aproblem that it is difficult to accurately grasp the shapes of thetrenches or the like. Japanese Patent Laid-Open No. 2006-295171, forexample, discloses a method to form interconnect by via-first method.

Japanese Patent Laid-Open No. 2006-073701 discloses a monitoring methodof etching rate by optical microscope when a film with mask is etched toexpose an underlying another film.

Japanese Patent Laid-Open No. 2003-229414, Japanese Patent Laid-Open No.2002-93870, National Publication of International Patent Application No.2006-506812 and National Publication of International Patent ApplicationNo. 2006-518942 disclose a method of irradiating light onto trenches orthe like and grasping shapes of the trenches or the like from reflectedlight (e.g., scatterometry method, OCD (Optical Critical Dimension)measurement. Scatterometry method(or OCD measurement) generally includesboth single wavelength-multi angle optical scattering method andmulti-wavelength-single angle optical scattering method one.

For example, Japanese Patent Laid-Open No. 2003-229414 and JapanesePatent Laid-Open No. 2002-93870 disclose a method of irradiating lightonto an insulating film in which a trench or the like is formed anddetecting reflected light from the insulating film. The shape of thetrench is grasped based on intensity of this reflected light.

According to this method, an interconnect layer is disposed below thetrench to be measured. The shape of the trench is measured using lightof a wavelength-band in which the utilized wavelength is larger thantwice the wiring space of the interconnect layer below the trench to bemeasured. This inhibits the light from passing through the interconnectlayer and prevents the unfavorable reflection from the materials and/orfeatures underlying the interconnect layer.

For example, the interconnect layer is composed of a striped tungstenmetal film having a width of 175 nm, thickness of 250 nm and a pitch of350 nm, and the wiring space is assumed to be 175 nm. Thewavelength-band of light used for measurement is assumed to be 900 nm to1600 nm.

However, the present inventor found out that the measuring methodsdisclosed in the related arts have the following problems.

When forming an interconnect layer, a trench is formed in an insulatingfilm, this trench is filled with a metal film, the metal film is thenpolished and removed by CMP (Chemical Mechanical polishing). In thiscase, erosion occurs as shown in FIG. 6.

In FIG. 6, reference numeral 901 denotes an insulating film, 902 denotesa metal film, 903 denotes an etching stopper film, 904 denotes aninterlayer insulating film and 905 denotes a cap film.

As shown in FIG. 6, steps are produced on the surface of the cap film905 at the top of the interconnect layer and the surface undulates dueto the influence of erosion.

When a trench is formed in such a condition, as shown in FIGS. 7A and7B, the shape of the trench 906 varies a great deal due to a differencein positions at which the opening of a mask is formed. Therefore, it isdifficult to fix the measuring condition of the trench 906 to a certaincondition, which affects productivity.

Furthermore, since the steps are produced on the surface of the cap film905 due to the influence of erosion, the steps remain on the surface ofthe cap film 905 even after the trench 906 is formed. In this case, themeasuring light is reflected by the steps and erroneous information islikely to occur when the trench 906 is measured.

SUMMARY

The present invention provides a semiconductor device comprising, afirst insulating film on a semiconductor substrate having a first regionand a second region, a light shielding film formed in the first regionand an interconnect film formed in the second region in the firstinsulating film and a second insulating film having a first concaveportion above the light shielding film in the first region and aninterconnect hole having a via hole and a second concave portion in thesecond region in the second insulating film on the first insulatingfilm, wherein an area of the light shielding film is overlapping an areaof the first plurality of concave portions.

According to the present invention, the area of the light shielding filmis overlapping the area of the first plurality of concave portions, andtherefore when the light shielding film is polished CMP, it is possibleto inhibit erosion from occurring in the first insulating film.

Erosion is generally a phenomenon that occurs when the interconnectpitch is narrow and densely arranged, and erosion occurs conspicuouslywhen the interconnect width is 1.6 μm or less.

On the contrary, as in the case of the present invention, the area ofthe light shielding film is overlapping the area of the first pluralityof concave portions and when the distance from the center to the outerperimeter of the light shielding film is assumed to be 2 μm or more andthe light shielding film having a large plane shape is formed, it ispossible to reliably prevent erosion from occurring.

In this way, even when an error occurs in the position at which theopening of a mask is formed when a concave portion is formed, it ispossible to suppress variations in the shape of the concave portionformed in the second insulating film. Therefore, it is possible toconduct measurement by determining a measuring condition to a certaincondition and improve productivity of the semiconductor device.

Furthermore, since the occurrence of erosion is prevented, it ispossible to inhibit steps from being formed on the surface of theinsulating film as in the cases of the related arts and preventmeasuring light from being reflected by the steps, producing measurementerrors when measuring the concave portion.

Furthermore, since the distance from the center to the outer perimeterof the light shielding film in a plan view is assumed to be 2 μm ormore, it is possible to effectively intercept information of layersunderlying the light shielding film when irradiating light, detectingreflected light and measuring the shape of the concave portion.

Furthermore, the present invention can also provide a method formanufacturing a semiconductor device as follows.

That is, the present invention can provide a method of manufacturing asemiconductor device comprising, forming a first insulating film on asemiconductor substrate having a first region and a second region,forming a first via hole in the second region in the first insulatingfilm, forming a reservoir region in the first region and a trench in thesecond region to connect with the first via to form a first interconnecthole in the first insulating film, forming a metal film on the firstinsulating film to fill the reservoir region and the first interconnecthole, performing polishing so as to leave the metal film in thereservoir region to form light shielding film and in the firstinterconnect hole to form interconnect, forming a second insulating filmon the first insulating film, forming a second via hole in the secondregion in the second insulating film, forming a first plurality ofconcave portions above the light shielding film in the first region anda second concave portion in the second region to connect with the secondvia to form a second interconnect hole in the second insulating film,wherein an area of the light shielding film is overlapping an area ofthe first plurality of concave portions.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view showing a semiconductor deviceaccording to a first embodiment of the present invention;

FIGS. 2A and 2B are cross-sectional views showing manufacturing steps ofa semiconductor device;

FIGS. 3A and 3B are cross-sectional views showing manufacturing steps ofa semiconductor device;

FIG. 4 is a plan view showing a relationship between a spot size ofmeasuring light, grooves and light shielding film;

FIGS. 5A and 5B show a semiconductor device according to a secondembodiment of the present invention;

FIG. 6 shows a related art of a semiconductor device; and

FIGS. 7A and 7B show a related art of a semiconductor device.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposes.

With reference now to the attached drawings, embodiments of the presentinvention will be explained below.

First Embodiment

A first embodiment of the present invention will be explained withreference to FIGS. 1 to 4.

First, an overview of a semiconductor device 1 of the present embodimentwill be explained.

As shown in FIG. 1, the semiconductor device 1 has a flat-film-shapedfirst light shielding film 12 formed in a first insulating film 11 and asecond insulating film 13 provided on the first light shielding film 12in which a plurality of concave portions 131 are formed. The pluralityof concave portions 131 of the second insulating film 13 is locatedabove the first light shielding film 12. The preferable area of thelight shielding film 12 is an area of the circle of 2 μm or more in theradius.

Next, the semiconductor device 1 will be explained in detail.

The semiconductor device 1 is formed like a wafer in which a pluralityof circuit regions is formed and a scribe region is formed between thecircuit regions.

In addition to the above described first insulating film 11, first lightshielding film 12 and second insulating film 13, the semiconductordevice 1 has a second light shielding film 14, a third insulating film15, a third light shielding film 16, a fourth insulating film, andfurther a semiconductor substrate 100 on which the first insulating film11 to the fourth insulating film 17 are multilayered.

Here, the semiconductor device in which only four insulating films aremultilayered is disclosed, but the multilayer structure of thesemiconductor device is not limited to this.

The first insulating film 11 is formed on a semiconductor substrate 100,for example, a silicon substrate such as a SiO2 film. The semiconductorsubstrate may be provided with semiconductor elements such as thetransistor 10 having the gate structure and the diffusion region in theinsulator layer 110 as indicated in FIG. 1.

The first insulating film 11 is formed extending over the circuit regionto the scribe region. At the location of the scribe region of this firstinsulating film 11, a reservoir region (first reservoir region) 111 isformed.

This reservoir region 111 has a distance from the center to the outerperimeter of 2 μm or more when seen from the substrate surface. Thereservoir region 111 according to the present embodiment has a planerectangular shape, and one side has, for example, 5 μm or more. Aboveall, one side preferably has 30 μm or more. Furthermore, one side morepreferably has 80 μm or less.

The first light shielding film 12 is embedded in this reservoir region111.

In a plan view seen from the substrate side, the distance from thecenter (center of gravity) to the outer perimeter of the first lightshielding film 12 is 2 μm or more. More specifically, the first lightshielding film 12 is formed according to the shape of the reservoirregion 111 and has a plane rectangular shape when seen from thesubstrate side. One side of the first light shielding film 12 is 5 μm ormore. Above all, the size of the first light shielding film 12 in theplan view seen from the substrate side is preferably equal to or greaterthan the light spot size of measuring light which will be describedlater, and more specifically, the distance from the center to the outerperimeter is preferably 15 μm or more. Furthermore, in the plan viewseen from the substrate side, the distance from the center to the outerperimeter of the first light shielding film 12 is preferably 40 μm orless.

According to the present embodiment, more specifically, the first lightshielding film 12 has a plane square shape and a length L2 of one sideis 60 μm as shown in FIG. 4. Though details will be described later,when the shape of the groove 131 is measured, an alignment error betweena stage on which the semiconductor device is set and an irradiationsection which irradiates measuring light is taken into consideration,the length L2 is set to be equal to or greater than the sum of the spotsize of measuring light and the alignment error.

Furthermore, the thickness of the first light shielding film 12 is, forexample, 0.1 μm to 1.2 μm.

This first light shielding film 12 is made of metal, copper or a copperalloy in the present embodiment.

The second insulating film 13 is provided on the first insulating film11 and is configured by including a low dielectric constant film havinga dielectric constant of, for example, 3.5 or less. The secondinsulating film 13 is a multilayer film in which, for example, a SiCNfilm 130A, SiOC film 130B and SiO2 film 130C are multilayered in thatorder.

The second insulating film 13 as well as the first insulating film 11 isformed extending over the circuit region to the scribe region. Areservoir region (second reservoir region) 132 and the plurality ofgrooves 131 (first concave portion) are formed in the part located inthe scribe region of this second insulating film 13. The reservoirregion 132 is formed at a predetermined distance from the plurality ofgrooves 131.

The reservoir region 132 and grooves 131 penetrate the SiO2 film 130C ofthe second insulating film 13 and reach a midway position of thethickness of the SiOC film 130B.

Furthermore, a plurality of trenches 133 having the same shape as thegroove 131 are formed in the circuit region of the second insulatingfilm 13. The array pattern of the trenches 133 is the same as the arraypattern of the grooves 131 and the width, length and height of thetrench 133 are all the same as those of the groove 131. The trench 135is a trench for an interconnect having a different width.

The groove 131 is slit-shaped and has, for example, a width (size in thehorizontal direction in FIG. 4) of 140 nm, array pitch of 140 nm, lengthof L1 (size in the vertical direction in FIG. 4) of 50 μm and height(depth) of 350 nm.

The plurality of grooves 131 are arranged equidistantly and regularlyand extend parallel to each other. Since the groove 131 and the trench133 have the same shape, the shape of the trench 133 can be grasped bygrasping the shape of the groove 131. Therefore, the plurality ofgrooves 131 can be said to be a mark for measuring the trenches.

The measuring mark formed of these plurality of grooves 131 preferablyhas a diameter equal to or greater than the size of a spot S ofmeasuring light as shown in FIG. 4. For example, when the spot size(diameter) of the measuring light is 30 μm, the distance from the planecenter of the measuring mark to the outer perimeter of the measuringmark is preferably 15 μm or more. By so doing, measurement can beperformed reliably.

In the present embodiment, the spot size of the measuring light is 30 μmand the length L1 of one side of the measuring mark formed of theplurality of grooves 131 (length in the array direction of the grooves131 and distance from the groove 131 on one side to the groove 131 onthe other side along the array direction) is 50 μm.

The plurality of grooves 131 are all located above the light shieldingfilm 12 in the aforementioned reservoir region 111, and are arrangedwithout sticking out of the light shielding film 12 in a plan view seenfrom the substrate surface side as shown in FIG. 4. Only one lightshielding film 12 is provided for the plurality of grooves 131, that is,one measuring mark.

As shown in FIG. 1, the grooves 131 are filled with a metal film 14A.This metal film 14A is similar to an interconnect film 14B with whichthe trenches 133 and 135 are filled and also the light shielding film14, which will be described later, and are made of, for example, copperor a copper alloy.

The metal film 14A in the grooves 131 is insulated from the lightshielding film 12 by the SiOC film 130B and SiCN film 130A of the secondinsulating film 13.

The reservoir region 132 has the same plane shape and size as those ofthe trench region 111. The height of the reservoir region 132 is greaterthan that of the reservoir region 111.

The light shielding film (second light shielding film) 14 is disposed inthis reservoir region 132. The plane size and shape of this lightshielding film 14 is the same as those of the light shielding film 12.Furthermore, the material of the light shielding film 14 is also thesame as that of the light shielding film 12.

The third insulating film 15 is formed on the second insulating film 13.

This third insulating film 15 has the same layer configuration as thatof the second insulating film 13 and is a multilayer film where, forexample, a SiCN film 150A, a SiOC film 150B and a SiO2 film 150C aremultilayered in that order.

The third insulating film 15 is also formed extending over the circuitregion to the scribe region as in the case of the first insulating film11 or the like. A reservoir region (third reservoir region) 152 and aplurality of grooves 151 (second concave portion) are formed in the partlocated in the scribe region of this third insulating film 15. Thereservoir region 152 is formed at a predetermined distance from theplurality of grooves 151.

The reservoir region 152 and grooves 151 penetrate the SiO2 film 150C ofthe third insulating film 15 and reaches a midway position in thethickness of the SiOC film 150B.

Furthermore, a plurality of trenches 153 are formed in the circuitregion of the third insulating film 15 as in the case of the grooves151. The array pattern of the trenches 153 is the same as the arraypattern of the grooves 151 and the width, length and height of thetrench 153 are all the same as those of the groove 151. The trench 155is a trench for an interconnect having a different width.

The groove 151 is formed in a slit shape and has, for example, a widthof 140 nm, array pitch of 140 nm, length of 50 μm and height of 350 nm.

The plurality of grooves 151 are all located above the light shieldingfilm 14 in the aforementioned reservoir region 132 and arranged withoutsticking out of the light shielding film 14 in a plan view seen from thesubstrate surface side.

The groove 151 is filled with a metal film 15A. This metal film 15A issimilar to an interconnect film 15B with which the trenches 153 and 155are filled and are made of, for example, copper or a copper alloy.

The metal film 15A in the grooves 151 is insulated from the lightshielding film 14 by the SiOC film 150B and the SiCN film 150A of thethird insulating film 15.

The reservoir region 152 has the same size and shape as those of thereservoir region 132.

The light shielding film (third light shielding film) 16 is disposed inthis reservoir region 152. The size and shape in a plan view of thislight shielding film 16 are the same as those of the light shieldingfilm 12. The material of the light shielding film 16 is also the same asthat of the light shielding film 12. The fourth insulating film 17 isprovided on the third insulating film 15.

This fourth insulating film 17 has the same layer configuration as thatof the second insulating film 13 and is a multilayer film in which, forexample, a SiCN film 170A, a SiOC film 170B and a SiO2 film 170C aremultilayered in that order.

As in the case of the first insulating film 11 or the like, the fourthinsulating film 17 is also formed extending over the circuit region tothe scribe region. A plurality of grooves (third concave portion) 171are formed in the part located in the scribe region of this fourthinsulating film 17.

The grooves 171 penetrate the SiO2 film 170C of the fourth insulatingfilm 17 and reach a midway position in the thickness of the SiOC film170B.

Furthermore, trenches 173 having the same shape as that of the grooves171 are formed in the circuit region of the fourth insulating film 17.The array pattern of the trenches 173 is the same as the array patternof the grooves 171 and the width, length and height of the trenches 173are all the same as those of the grooves 171.

The trench 175 is a trench for an interconnect having a different width.

The groove 171 is slit-shaped and has, for example, a width of 140 nm,array pitch of 140 nm, length of 50 μm and height of 350 nm.

The plurality of grooves 171 are all located above the light shieldingfilm 16 in the aforementioned reservoir region 152 and located withoutsticking out of the light shielding film 16 in a plan view seen from thesubstrate surface side.

This groove 171 is filled with a metal film 17A. This metal film 17A issimilar to that of an interconnect film 17B with which the trenches 173and 175 are filled and are made of, for example, copper or a copperalloy.

The metal film 17A in the groove 171 is insulated from the lightshielding film 16 by the SiOC film 170B and SiCN film 170A of the fourthinsulating film 17.

In the above described semiconductor device, the plurality of grooves131 are disposed above the light shielding film 12, the light shieldingfilm 16 is disposed above the plurality of grooves 131 and the grooves171 are disposed above the light shielding film 16.

On the other hand, the grooves 151 are formed above the light shieldingfilm 14.

Next, the method of manufacturing the semiconductor device 1 will beexplained with reference to FIGS. 2 and 3.

First, the transistor 10 having a gate structure and a diffusion regionand an insulating layer 110 and the insulating film 11 are formed on thesemiconductor substrate 100.

Next, the insulating film 11 is selectively removed by etching and thereservoir region 111 is formed. The reservoir region 111 is then filledand a metal film (light shielding layer) is formed so as to cover thesurface of the insulating film 11. The metal film is then polished byCMP and only the metal film is left in the reservoir region 111. In thisway, the light shielding film 12 is formed (FIG. 2A). In the same time,an interconnect 121 is formed.

Next, the insulating film 13 is provided on the insulating film 11.Continually, insulating film 13 is etched to form a via hole 134 with amask in the circuit region. Because the insulator film 130A is notetched when the via hole is formed, it may be done to measure the shapeof the via hole as described in the second embodiment.

Further, the mask to form the trench connecting with the via hole 134,the reservoir region 132 and grooves 131 is formed on the insulatingfilm 13. The insulating film 13 is then selectively removed by etching,the reservoir region 132 and grooves 131 are formed in the scribe regionof the insulating film 13 and the interconnect hole 136 having a trench133 and a via hole 134 is formed in the circuit region (FIG. 2B).

Next, the plurality of grooves 131 are irradiated with light, reflectedlight is detected and the shape of the grooves 131 is acquired from thedetected reflected light.

Here, examples of the method of acquiring the shape of the grooves 131from the reflected light include a scatterometry method (lightscattering measuring method). According to this method, a database iscreated beforehand which associates the shape of the grooves (e.g.,depth (height) of the grooves, width of the grooves, angle of the sidewall with respect to the bottom surface of the grooves or the like) withthe waveform of reflected light. Light is irradiated onto the grooves131 and the waveform of the reflected light is compared with thewaveform in the database. When the waveform of the reflected lightmatches the waveform in the database, the shape of the groovesassociated with the waveform in the database is understood as an optimalvalue of the actual shape of the grooves.

Since the plurality of grooves 131 have a size and shape similar tothose of the trenches 133 formed in the circuit region and also have asimilar array pattern, when the grooves 131 have a desired shape, it ispossible to judge that the trenches 133 formed in the circuit regionhave a desired shape.

On the other hand, when the grooves 131 do not have the desired shape,the trenches 133 in the circuit region are also estimated not to have adesired shape. Semiconductor devices in which the trenches 133 in thecircuit region do not have the desired shape are excluded so as not tomove to the next step.

Furthermore, the difference between the shape of the grooves 131 and thedesired shape is acquired and etching conditions such as an etching timeare adjusted. In this way, a desired shape is obtained when trenches 133in the next semiconductor device are formed.

Next, the reservoir region 132, grooves 131 and the interconnect hole136 having a trench 133 and a via hole 134 are filled and a metal film(light shielding layer) for covering the surface of the insulating film13 is formed. Then, after polishing by CMP, this metal film remains inthe reservoir region 132, grooves 131 and the interconnect hole 136having a trench 133 and a via hole 134. In this way, the light shieldingfilm 14, metal film 14A and interconnect 14B in the grooves 131 areformed.

Next, as shown in FIG. 3A, the insulating film 15 is provided on theinsulating film 13. Continually, insulating film 15 is etched to form avia hole 154 with a mask in the circuit region. Because the insulatorfilm 150A is not etched when the via hole is formed, it may be done tomeasure the shape of the via hole as described in the second embodiment.

Further, the mask to form the trench connecting with the via hole 154,the reservoir region 152 and grooves 151 is formed on the insulatingfilm 13. After that, the insulating film 15 is selectively removed byetching and reservoir region 152 and grooves 151 are formed in thescribe region of the insulating film 15 and the interconnect hole 156having a trench 153 and a via hole 154 is formed in the circuit region.

The shape of the groove 151 is acquired using the same method as thatfor acquiring the shape of the groove 131 and it is judged whether ornot the trenches 153 have a desired shape. When the trenches 153 do nothave the desired shape, this semiconductor device is excluded so as notto move to the next step.

Furthermore, the difference between the shape of the groove 151 and thedesired shape is acquired and etching conditions such as an etching timeare adjusted. When the trenches 153 are formed in the next semiconductordevice, this allows the trenches 153 to have the desired shape.

Next, the metal film (light shielding layer) is formed to fill thereservoir region 152, grooves 151 and trenches 153 and cover the surfaceof the insulating film 15. Then, after polishing by CMP, this metal filmremains in the reservoir region 152, grooves 151 and the interconnecthole 156 having a trench 153 and a via hole 154. In this way, the lightshielding film 16, the metal film 15A in the grooves 151 andinterconnect 15B are formed.

Next, as shown in FIG. 3B, the insulating film 17 is provided on theinsulating film 15.

After the masks to form a via hole 174 and a trench are formed on theinsulating film 17, as described above, the insulating film 17 is thenselectively removed by etching and the grooves 171 are formed in thescribe region of the insulating film 17 and the interconnect hole 176having a trench 173 and a via hole 174 are formed in the circuit region.It may be done to measure the shape of the via hole 174 as described inthe second embodiment.

The shape of the groove 171 is acquired using the same method as foracquiring the shape of the grooves 131 and it is judged whether or notthe trenches 173 have the desired shape. When the trenches 173 do nothave the desired shape, this semiconductor device is excluded so as notto move to the next step.

Furthermore, the difference between the shape of the groove 171 and thedesired shape is acquired and etching conditions such as an etching timeare adjusted. When the trenches 173 are formed in the next semiconductordevice, this allows the trenches 173 to have the desired shape.

Next, the metal film (light shielding layer) is formed so as to fill thegrooves 171 and the interconnect hole 176 having a trench 173 and a viahole 174, and cover the surface of the insulating film 17. Then, afterpolishing by CMP, this metal film remains in the grooves 171 and theinterconnect hole 176 having a trench 173 and a via hole 174. In thisway, the metal film 17A in the grooves 171 and the interconnect film 17Bin the interconnect hole 176 having a trench 173 and a via hole 174 areformed.

The semiconductor device 1 is completed in the above described steps.

Next, the operations and effects of the present embodiment will beexplained.

According to the present embodiment, since the distance from the centerto the outer perimeter in a plan view of the light shielding films 12,14 and 16 is assumed to be 2 μm or more, it is possible to suppress theoccurrence of erosion in the insulating films 11, 13 and 15 when thelight shielding films 12, 14 and 16 are formed by polishing by CMP.Especially, the light shielding films 12, 14 and 16 are singly arrangedonly one each and the respective light shielding films are not arrangedin the plural, and it is thereby possible to reliably suppress theoccurrence of erosion.

Therefore, even if there is an alignment error in the arrangement of theopenings of masks to form the grooves 131, 151 and 171, variations inthe shapes of the grooves 131, 151 and 171 are suppressed. Therefore,measurement can be conducted with the measuring conditions set tocertain conditions and productivity can be improved.

Furthermore, since the occurrence of erosion in the insulating film 11can be prevented, it is possible to prevent steps from being formed dueto the influence of erosion on the surface of the insulating film 13formed on the insulating film 11.

When the grooves 131 are measured, this can inhibit the measuring lightfrom being reflected by steps causing errors in the measured value ofthe grooves 131.

Similar effects can also occur when the grooves 151 and 171 are formed.

Furthermore, the distance from the center to the outer perimeter of thelight shielding film 12 in the plan view is set to 2 μm or more. Whenthe groove pattern is irradiated with light, the reflected light isdetected and the shape of the grooves 131 is measured, this can preventthe reflected light from layers underlying the light shielding film 12from mixing up. This allows the shape of the grooves 131 to beaccurately grasped.

Since the distance from the center to the outer perimeter of the lightshielding films 14 and 16 in the plan view is also set to 2 μm or more,the shape of the grooves 151 and 171 can also be grasped accurately asin the case of the grooves 131.

Furthermore, according to the present embodiment, the light shieldingfilm 12 has a size equal to or more than the spot size of lightirradiated onto the grooves 131. According to a scatterometry method,since the spot size of light is generally 30 μm, setting the distancefrom the center to the outer perimeter of the light shielding film 12 ina plan view to 30 μm or more can prevent light from passing below thelight shielding film 12.

In this way, it is possible to prevent information on layers underlyingthe light shielding film 12 from being included in the reflected lightfrom the grooves 131 and accurately grasp the shape of the grooves 131.

Similar effects can also be obtained with the light shielding films 14and 16 because the light shielding films 14 and 16 are set to a sizeequal to or greater than the spot size of light irradiated onto thegrooves 151 and 171.

Furthermore, in the measuring device that measures grooves, the presentembodiment takes an alignment error between the stage for setting thesubstrate on which the insulating films or the like are multilayered andthe irradiation section that irradiates measuring light intoconsideration and sets the size of the light shielding films 12, 14 and16 in the plan view to a size equal to or greater than the sum of thespot size of the measuring light and the alignment error, and canthereby grasp the shapes of the grooves 131, 151 and 171 moreaccurately.

On the other hand, the present embodiment sets upper limits of the sizesof the light shielding films 12, 14 and 16 such that the distance fromthe center to the outer perimeter of the light shielding films 12, 14and 16 is 40 μm, and can thereby prevent the scribe region from beingnarrowed by the light shielding films 12, 14 and 16.

Furthermore, the present embodiment forms the light shielding films 12,14 and 16 and grooves 131, 151 and 171 in the scribe region, and canthereby prevent the circuit region from being narrowed by the lightshielding films 12, 14 and 16 and grooves 131, 151 and 171.

Furthermore, the present embodiment arranges the plurality of grooves131 above the light shielding film 12, arranges the light shielding film16 above the plurality of grooves 131 and arranges the grooves 171 abovethe light shielding film 16. Furthermore, the present embodimentarranges the grooves 151 above the light shielding film 14.

Adopting such a configuration minimizes the space in a plan view inwhich the grooves and light shielding films are formed. Various markssuch as alignment marks may be formed in the scribe region. When thelight shielding films and grooves are formed in the scribe region, it ispossible to effectively use the scribe region for a variety ofapplications without narrowing the scribe region.

Second Embodiment

A second embodiment of the present invention will be explained withreference to FIG. 5.

In the above described embodiment, gratings 131, 151 and 171 are formed,but in the present embodiment, a plurality of cylindrical holes 231 areformed instead as shown in FIG. 5.

The plurality of holes 231 are formed in the scribe region as in thecase of the above described embodiment, and via holes (not shown) havinga size similar to that of the holes 231 are formed in the circuit regionof the insulating film 13. The array pattern of the via holes is thesame as the array pattern of the holes 231.

Furthermore, as shown in FIG. 5B, the plurality of holes 231 are formedso as not to stick out of the light shielding film 12 in a plan view.

The holes 231 are filled with a metal film 24A. This metal film 24A issimilar to the metal film 14A and is made of a material similar to thatfor the vias with which the via holes are filled.

The rest of aspects are the same as those of the above describedembodiment.

The present embodiment can exert effects similar to those in the abovedescribed embodiment and can further exert the following effects.

To acquire the shape of a via hole (e.g., size of the bottom of the viahole), a length measuring SEM (Scanning Electron microscope) isconventionally used. In contrast, use of a scatterometry method as inthe case of the present embodiment does not take much time formeasurement.

The present invention is not limited to the aforementioned embodiments,but modifications, improvements or the like within the scope in whichthe object of the present invention can be achieved are included in thepresent invention.

For example, when measuring the shape of the grooves 131 or the like,the above described embodiments compare the waveform of reflected lightfrom the grooves 131 with waveforms in the database beforehand anddetermine the shape of the grooves from the matching waveform in thedatabase.

However, the method of measuring the shape of the grooves 131 or thelike is not limited to such a method, but it is also possible to graspthe shape of the grooves 131 or the like based on the intensity ofreflected light from the grooves 131 or the like as in the case ofPatent Document 1.

Furthermore, the above described embodiments form the grooves 131 or thelike and a light shielding film 12 or the like in the scribe region, butthe present invention is not limited to this and these may also beformed in the circuit region.

Furthermore, the first embodiment assumes that the plurality of grooves131 are arranged above the light shielding film 12, the light shieldingfilm 16 is arranged above the plurality of grooves 131 and the grooves171 are arranged above the light shielding film 16, but the presentinvention is not limited to such a structure. That is, the lightshielding film 16 may also be provided at a location shifted from thelocation above the plurality of grooves 131.

Furthermore, the above described embodiments arrange the plurality ofgrooves 131 so as not to stick out of the light shielding film 12 in theplan view seen from the substrate surface side, but the presentinvention is not limited to this and the grooves 131 may also bearranged such that parts of the grooves 131, for example, an end in thelongitudinal direction of the grooves 131 sticks out of the lightshielding film 12.

However, by arranging the plurality of grooves 131 so as not to stickout of the light shielding film 12 as in the cases of the abovedescribed embodiments, it is possible to reliably intercept theinformation of layers underlying the light shielding film 12 whenmeasuring the shape of the grooves 131.

EXAMPLES

Next, examples of the present invention will be explained.

Example 1

As in the case of the first embodiment, the light shielding film 12 wasformed in the insulating film 11. The light shielding film 12 wasassumed to be a square of 4 μm per side. CMP was applied when the lightshielding film 12 was formed, but no erosion occurred.

Furthermore, the insulating film 13 was provided on the light shieldingfilm 12, but the surface of the insulating film 13 was flat and noprojections and depressions were formed. The plurality of grooves 131and trenches 133 were then formed in the insulating film 13.

The width (length in the short side direction) of the groove 131 and atrench 133 was 140 nm, the height was 370 nm and the depth (length inthe long side direction) of the groove 131 and a trench 133 was 50 μm.

The length L1 of one side of the square measuring mark made up of theplurality of grooves 131 was 50 μm.

No erosion occurs if the size of the light shielding film 12 isdetermined such that the distance from the center to the outer perimeteris 2 μm or more. Therefore, even when an error occurs in the locationwhere the opening of the mask is formed when the plurality of grooves131 and trenches 133 are formed, variations in the shapes of theplurality of grooves 131 and trenches 133 are suppressed. Furthermore,since no projections and depressions are formed on the surface of theinsulating film 13, it is understandable that it is possible to suppressthe reflection of measuring light by steps and the occurrence ofmeasurement errors.

Furthermore, the grooves 131 were measured using a scatterometry method.The spot size of measuring light was assumed to be 30 μm. The grooves131 could be measured in Example 1.

Example 2

As in the case of the first embodiment, the light shielding film 12 wasformed in the insulating film 11. The light shielding film 12 wasassumed to be a square having the length L2 of 60 μm per side. Theinsulating film 13 was provided on the light shielding film 12 and theplurality of grooves 131 and trenches 133 were formed in the insulatingfilm 13.

The length L1 per side of the square measuring mark made up of theplurality of grooves 131 was assumed to be 50 μm. The grooves 131 weremeasured using a scatterometry method. The spot size of the measuringlight was set to 30 μm here.

Table 1 shows the depth of the bottom of the plurality of groove 131measured using the scatterometry method and the depth of the pluralityof grooves 131 measured using a cross-sectional SEM as in the case ofthe first embodiment.

TABLE 1 Measured value (nm) using scatterometry method Cross-sectionalSEM value (nm) 378.6 377 376.5 377 388.4 390 378.1 380 396.2 394 388.9387 377.3 380 380.7 377 390.3 390This table shows that accurate measurement is made possible by providingthe light shielding film.

CMP was applied when the light shielding film was provided but noerosion was found.

Example 3

In Example 3, the light shielding film 12 was formed in the insulatingfilm 11 as in the case of the second embodiment. The light shieldingfilm 12 was assumed to be a square having the length L2 of 60 μm perside. The insulating film 13 was provided on the light shielding film 12and a plurality of holes 231 and via holes were formed in the insulatingfilm 13.

The length L1 of one side of the square measuring mark made up of theplurality of holes 231 (length from the hole 231 at an end of one sideof the square to the hole 231 at the other end) was assumed to be 50 μm.

The rest of aspects are the same as those in Example 2.

The widths of the bottom of 17 holes 231 in the plane of thesemiconductor substrate were measured using a scatterometry method.Furthermore, the widths of the bottom of 17 holes 231 were measuredusing a length measuring SEM.

Table 2 shows the results.

TABLE 2 Measured value (nm) using scatterometry Cross-sectional methodSEM value (nm) Mean value (nm) 115.8 115.8 3σ (nm) 5.2 3.2 Max (nm)118.0 117.6 Min (nm) 112.2 113.7

This table shows that accurate measurement is made possible by providingthe light shielding film.

CMP was applied when the light shielding film was provided, but noerosion was found.

Comparative Example 1

An insulating film was provided on a semiconductor substrate andtrenches having a width of 175 nm, a height of 250 nm and a pitch of 350nm were formed in this insulating film. Next, a tungsten metal film wasformed so as to fill these trenches and cover the insulating film andwas then polished for planarization.

In this case, erosion occurred in the insulating film and projectionsand depressions were formed on the surface of the insulating film.

Next, a second insulating film was provided on the insulating film andtrenches having a width of 175 nm, a height of 250 nm and a pitch of 350nm were formed in the second insulating film. Projections anddepressions were formed on the surface of the second insulating film dueto an influence of erosion.

When the shape of the trenches was measured as in the case of Example 2,a large difference between the measured value using a SEM and themeasured value using scatterometry method was observed due to theprojections and depressions on the surface of the second insulatingfilm.

1. A method of manufacturing a semiconductor device, comprising:providing a database including a relationship between shapes ofreference grooves and corresponding reference waveforms of lightreflected by the reference grooves; irradiating light on actual groovesand detecting an actual waveform of light reflected by the actualgrooves; matching the actual waveform to one of the reference waveformsin the database to determine a shape of the actual grooves, wherein theactual grooves are formed on a light shielding film in a test region;and wherein the actual grooves are formed during a step in which aninterconnect hole having a via hole and a trench are formed.
 2. Themethod of manufacturing a semiconductor device according to claim 1,wherein the actual grooves and the trench are of substantially equalshape.
 3. The method of manufacturing a semiconductor device accordingto claim 1, wherein etching conditions are adjusted based on adifference between the shape of reference grooves and the actualgrooves.
 4. The method of manufacturing a semiconductor device accordingto claim 1, comprising a further step of determining whether there is adifference between the shape of reference grooves and the actualgrooves, and excluding a wafer from further processing if saiddifference is detected.
 5. The method of manufacturing a semiconductordevice according to claim 1, wherein another light shielding film isformed during a step in which the interconnect hole in the test regionis formed.
 6. The method of manufacturing a semiconductor deviceaccording to claim 1, further comprising forming a metal film that fillsthe interconnect hole.